Error correction code (ECC) memory is a type of computer data storage that can detect and correct most common kinds of internal data corruption. ECC memory may be used in computers where data corruption cannot be tolerated under any circumstances, such as for scientific or financial computing. Conventionally, ECC is added to memory data contents in order to provide a means for checking the memory data when the memory is read. Typical ECC and related logic allow for single bit errors to be corrected and at least two errors to be detected. Accordingly, ECC memory maintains a memory system effectively free from single bit errors.
The general idea for achieving error detection and correction is to add some redundancy (i.e., some extra data) to a message, which receivers can use to check consistency of the delivered message, and to recover data determined to be corrupted. Error-detection and correction schemes can be either systematic or non-systematic. In a systematic scheme, the transmitter sends the original data, and attaches a fixed number of check bits (or parity data), which are derived from the data bits by some deterministic algorithm. If only error detection is required, a receiver can simply apply the same algorithm to the received data bits and compare its output with the received check bits. If the values do not match, an error has occurred at some point during the transmission (e.g., during the writing and reading process into a memory). In a system that uses a non-systematic code, the original message is transformed into an encoded message that has at least as many bits as the original message.
The ECC logic associated with generating the correct codes or check bits and then decoding the codes or check bits and correcting the data can be difficult to test thoroughly using normal automatic test pattern generation techniques. For example, the ECC logic typically comprises a deep logic tree of XOR gates. The resulting testing coverage of stuck faults and/or defects within the ECC logic can be limited with traditional random test patterns. If defects escape logic testing during manufacturing, the defects may pose a serious risk to quality levels of shipped product in end user systems. Memory data can become corrupted by these defects, or the defects may (at the very least) prevent detection and correction of errors within the memory data.
Furthermore, it may be advantageous to test and repair all memory bits within the ECC logic that are conventionally ignored or bypassed. This results in a high quality memory test. However, in order to improve the shipped product quality level of in-system memory built in self test (BIST) it may be advantageous to test the memories with the ECC logic turned on such that the in-system memory is testing the memories in a similar manner in which the memories would be used in the computing system. Therefore, any minor fails induced by in-system conditions (e.g., noise, power supply irregularities, etc.) may be corrected by the ECC logic and the in-system memory BIST may only report issues (and optionally make repairs) if there are drastic issues that are un-correctable by the ECC logic.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.